In BCD arithmetic, at least four binary bits are needed to represent the numbers from 0 to 9. There are sixteen possible bit combinations using four binary bits, but only ten (i.e, 0 to 9) are valid BCD digits. Traditionally, BCD adder circuits adjust the binary sum after the addition has been completed if the value is more than nine (i.e., 10012). For example, whenever the unadjusted sum of two BCD digits produced a carry out (i.e., when the sum exceeds 10012), the sum is corrected by adding 01102.
A known BCD adder, described in “Logic and Computer Design Fundamentals”, M Morris Mano and Charles R Kime, Pearson Educational Asia, second edition, 2001 is shown in FIG. 1. The BCD adder circuit 5 uses a four-bit binary adder 6 to add two BCD operands A(3) to A(0) and B(3) to B(0), and an input carry Cin to produce an intermediate sum Z(3) to Z(0). The adder circuit 6 also includes two levels of logic gates 7, 8, 9 to calculate the BCD carry output Cout from the intermediate sum. If there is a BCD carry, a correction factor of 01102 is added with the intermediate sum using a further binary adder 10.
The BCD adder circuit 5 shown in FIG. 1 thus uses 10 levels of gates to perform a 4-bit addition. For a 16-bit adder circuit, the corresponding binary adder circuit requires 16 levels of gates. However the critical path is the generation of the carry Cout, and gate levels required to implement this is 22 for 16-bit BCD addition.
Another BCD adder circuit is taught in U.S. Pat. No. 4,805,131 (Adlietta et al, assigned to Digital Equipment Corporation), issued on Feb. 14, 1989. The BCD adder of Adlietta et al has three stages. In the first stage, 01102 is added with the input BCD operands without considering the input carry. In the second stage the sum and carry vectors are added using a carry look ahead network to generate final carry and propagate vectors. In the third stage a correction circuit adds 10102 if needed.
The logic terms in the calculation of a FINAL_CARRY vector increases as the number of bits of the BCD operands increases. Also, the carry vector calculated is propagated through every bit position. The bit terms of the FINAL_CARRY vector must propagate through every bit position. As the bit position increases from least significant bit position 0 through most significant bit position 15, the number of logical terms required to produce the terms of the FINAL_CARRY vector also increases. Therefore, more sophisticated logic gates are required to produce the more significant bit terms and keep the number of logic levels and associated delay to a minimum.
For 16-bit BCD addition the BCD adder circuit of Adlietta et al uses only 12 gate levels compared to 22 gate levels in the BCD adder circuit of FIG. 1. But the logic terms required for the implementation of the FINAL_CARRY of BCD adder of Adlietta et al is much higher. Also, when the number of bits of the BCD operands increase, the logic terms for calculating the FINAL_CARRY also increases, which makes the implementation complex for more than 16-bits. There also is no reusability, meaning extending similar structures when the number of bits of the input BCD operands increases.
There remains a need for BCD addition circuits with lesser a number of gate levels as well as lesser number of logic terms without requiring any sophisticated logic gates. There is also a need to increase the reusability of logic gates in such adders.